The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for reducing energy consumption of set associative caches by reducing checked ways of the set association when possible.
As is described in Powell et al., “Reducing Set-Associative Cache Energy via Way-Prediction and Selected Direct-Mapping,” Proceedings of the 34th international Symposium on Microarchitecture (MICRO 34), 2001, high performance caches dissipate significant dynamic energy due to charging and discharging of highly capacitive bit lines and sense amps. As a result, caches account for a significant fraction of the overall chip dynamic energy.
A direct mapped cache is one in which data/instructions associated with a particular address may be stored in only one location within the cache. While these caches provide a fastest possible access to the instructions/data assuming that they are in the cache, if the instructions/data are not in the cache, then a cache miss and its associated handling overhead of evicting existing instructions/data in the cache and replacing them with the needed instructions/data from a lower level cache or main memory must be endured. Such cache miss handling significantly slows the performance of the processor. Direct mapped caches, in which there is only one location in the cache where the particular instruction/data for an address may be present, often encounter cache misses.
To achieve lower cache miss rates, modern microprocessors employ set associative caches as opposed to direct mapped caches. In a set associative cache the instructions/data may be stored in multiple locations within the cache, i.e. in an N-way associative cache, the instructions/data may be located in anyone of N locations within the N-way associative cache. Since the instructions/data may be available from multiple locations within the cache, there is a smaller likelihood of a cache miss occurring and thus, the overhead associated with handling a cache miss may be avoided more often. However, with these set associative caches, when a check of the cache is performed to access instructions/data corresponding to an address, all of the possible locations where the instruction/data may be located, i.e. all of the “ways” of the set associative cache, must be checked. Checking more locations in the cache requires more power, chip area, and time.